The present invention relates to a dynamic RAM (random access memory) and an information processing system using the same. More particularly, the invention relates to a dynamic RAM capable of mass storage, and an information processing system utilizing such a RAM.
A typical sense amplifier compensating for fluctuating threshold voltages of MOSFET's in a dynamic RAM is disclosed illustratively in Japanese Utility Model Laid-Open No. SHO/56-21897, and another sense amplifier of the same kind is discussed in the minutes 2-288 of the 1983 General Meeting of IECE (Institute of Electronics and Communication Engineers of Japan). The former sense amplifier is one having amplifier MOSFET's connected in a diode formation during the pre-charge period so as to pre-charge the bit lines from the source side. The latter sense amplifier involves separating the sources of amplifier MOSFET's so as to execute initial amplification through capacitive coupling.
In such a dynamic RAM, the sense amplifier is composed of CMOS circuits for reduced power dissipation. Putting the sense amplifier in the CMOS circuit arrangement entails setting the pre-charge potential of the bit lines to half the operating voltage. This means that the CMOS-based sense amplifier cannot be of the type disclosed in Japanese Utility Model Laid-Open No. SHO/56-21897, i.e., the sense amplifier having the bit lines pre-charged with the supply voltage. The fact that the amplifier MOSFET's comprise P- and N-channel MOSFET's poses some problems. One problem is that a one-to-one correspondence cannot be ensured between the offset voltage of the sense amplifier on the one hand, and the fluctuation of the threshold voltage of the N- and P-channel MOSFET's on the other. Another problem is the growing difficulty in performing pre-charging because of the conflict between the N- and the P-channel MOSFET's.
There is a major disadvantage to the sense amplifier discussed in the above minutes of the 1983 General Meeting of IECE. That is, the setup in which the sense amplifier operates on capacitive coupling requires incorporating a huge capacitance into that amplifier. The scheme is not realistic because of the following reason: in a dynamic RAM, a large number of memory cells are connected to each bit line to enlarge the storage capacity. This entails a relatively large parasitic capacitance of the bit lines. To ensure a sufficiently large bit line potential based on capacitive coupling requires furnishing a considerably massive capacitor arrangement. Incorporating such a capacitance arrangement into the sense amplifier is impossible to achieve from the viewpoint of circuit integration.